Clocks and Timers CDCE18005 5/10 Outputs Clock Buffer with Divider

Features

• Universal Input Buffers That Accept LVPECL, LVDS, or LVCMOS Level Signaling
• Fully Configurable Outputs Including Frequency, Output Format, and Output Skew
• Output Multiplexer That Serves as a Clock Switch Between the Three Reference Inputs and the Outputs
• Clock Generation Via AT-Cut Crystal
• Integrated EEPROM Determines Device Configuration at Power-up
• Low Additive Jitter Performance
• Universal Output Blocks Support up to 5 Differential, 10 Single-ended, or Combinations of Differential or Single-ended:
  • Low Additive Jitter
  • Output Frequency up to 1.5 GHz
  • LVPECL, LVDS, LVCMOS, and Special High Output Swing Modes
  • Independent Output Dividers Support Divide Ratios from 1—80
  • Independent limited Coarse Skew Control on all Outputs
• Flexible Inputs:
  • Two Universal Differential Inputs Accept Frequencies up to 1500 MHz (LVPECL), 800 MHz (LVDS), or 250 MHz (LVCMOS).
  • One Auxiliary Input Accepts Single Ended Clock Source or Crystal. Auxiliary Input Accepts Crystals in the Range of 2 MHz—42 MHz or an LVCMOS Input up to 75 MHz.
  • Clock Generator Mode Using Crystal Input.
• Typical Power Consumption 1.0W at 3.3V (see Table 27)
• Integrated EEPROM Stores Default Settings; Therefore, The Device Powers up in a Known, Predefined State.
• Offered in QFN-48 Package
• ESD Protection Exceeds 2kV HBM
• Industrial Temperature Range -40°C to 85°C
• APPLICATIONS
  • Data Converter and Data Aggregation Clocking
  • Wireless Infrastructure
  • Switches and Routers
  • Medical Electronics
  • Military and Aerospace
  • Industrial
  • Clock Fan-out

Description

The CDCE18005 is a high performance clock generator and distributor featuring a high degree of configurability via a SPI interface, and programmable start up modes determined by on-board EEPROM. Specifically tailored for buffering clocks for data converters and high-speed digital signals, the CDCE18005 achieves low additive jitter in the 50 fs RMS⁽¹⁾ range. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (up to 1.5 GHz⁽²⁾) and skew relationship via a programmable delay block. If all outputs are configured in single-ended mode (e.g. LVCMOS), the CDCE18005 supports up to ten outputs. Each output can select one of three clock input sources. The input block includes two universal differential inputs which support frequencies up to 1500 MHz and an auxiliary single ended input that can be connected to a CMOS level clock or configured to connect to an external crystal via an on board oscillator block.

⁽¹⁾12 kHz to 20 MHz integration bandwidth.

⁽²⁾ Maximum output frequency depends on the output format selected.

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