Logic P82B96 Dual Bidirectiional Bus Buffer

• Operating Power-Supply Voltage Range of 2 V to 15 V
• Can Interface Between I²C Buses Operating at Different Logic Levels (2 V to 15 V)
• Supports Bidirectional Data Transfer of I²C Bus Signals
• Allows bus capacitance of 400 pF on the Main I²C Bus (Sx/Sy Side) and 4000 pF on the Transmission Side (Tx/Ty)
• Outputs on the Transmission Side (Tx/Ty) Have High Sink Capability for Driving Low-Impedance or High-Capacitive Buses
• I²C Bus Signals Can Be Split Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry) Signals for Interface With Optoelectrical Isolators and Similar Devices That Need Unidirectional Input and Output Signal Paths
• 400-kHz Fast I²C Bus Operation Over at Least 20 Meters of Wire
• Low Standby Current Consumption
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 3500-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The P82B96 is a bipolar device that supports bidirectional data transfer between the normal I²C bus and a range of other bus configurations with different voltage and current levels. It can function as the interface without any limitations on the normal I²C operation and clock speed.

One of the advantages of the P82B96 is that it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I²C nodes are not apparent to other I²C buses (or nodes). This device also adds minimal loading to I²C node where it is positioned. Any restrictions on the number of I²C devices in a system, or the physical separation between them, are virtually eliminated.

The P82B96 easily can transmit SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (optocoupling), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an alternative bidirectional signal line with I²C properties.

Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bidirectional I²C signals do not allow any direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A regular I²C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a regular I²C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, such as the PCA9515A.

The Sx/Sy side is intended only for, and compatible with, the normal I²C logic voltage levels of I²C master and slave devices or Tx/Rx signals of a second P82B96, if required. The Tx/Rx and Ty/Ry I/O pins use the standard I²C logic voltage levels of all I²C parts. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.