New 90nm LatticeECP2M FPGAs First to Offer Embedded SERDES for High Volume FPGA Family

– Ground Breaking Family Establishes
New Price/Performance Standard for Low Cost, High Volume FPGAs –

HILLSBORO, OR - SEPTEMBER 18, 2006 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the LatticeECP2M™ FPGA family, the industry’s first low cost FPGAs offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2™ low cost architecture, the new LatticeECP2M family also has been developed on advanced 90nm CMOS technology utilizing 300mm wafers. Previously, high-speed embedded SERDES serial I/O with speeds over 3Gbps has been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment. Priced at approximately one-third the cost of competitive SERDES-based FPGAs, the ECP2M FPGA family effectively bridges the price/performance gap between low cost and high-end FPGAs.

The LatticeECP2M devices also have dramatically increased on-chip memory capacity to support higher bandwidth, SERDES-based applications. LatticeECP2M Embedded Block RAM capacity ranges from 1.2 Mbit up to 5.3 Mbits, representing up to a 400% increase over competitive low cost architectures. Both the LatticeECP2 and LatticeECP2M FPGA families offer a comprehensive array of features that includes 375 MHz block level performance, 18x18 multipliers, embedded memory, pre-engineered 400 Mbps DDR2 memory interface support, full-rate (10Gbps+) SPI4.2 support, configuration bitstream encryption and dual-boot configuration support. With the addition of 4 to 16 channels of 3.125 Gbps SERDES, the LatticeECP2M FPGAs are an innovative response to the broad range of customers who have been clamoring for low cost SERDES capability for PCI Express and Ethernet based chip-to-chip and small form factor backplane applications.

“The LatticeECP2M family charts a new course within the low cost FPGA segment, and sets Lattice apart in terms not only of our product innovation but also our ability to bring heightened value to our customers,” said Steve Skaggs, Lattice CEO. “These devices redefine what a low cost FPGA should be, and they will change how customers evaluate FPGAs for their high volume designs.”

"Our customers enthusiastically embraced the Economy Plus concept when we introduced it with our first-generation LatticeECP family," said Stan Kopec, Lattice corporate vice president of marketing. "Now, Lattice is breaking with convention by delivering the lowest cost SERDES-based FPGAs in the industry. The LatticeECP2M family and our recently announced Extreme Performance LatticeSC™ devices now provide the industry’s most complete portfolio of high-speed embedded SERDES solutions."

The LatticeECP2M family will include five devices ranging in density from 20K LUTS to 95K LUTS. The number of 18x18 multipliers in the LatticeECP2M family also has been increased and now ranges from 24 to 168. Each device provides two Delay Locked Loops (DLLs) and eight Phase Locked Loops (PLLs) for timing control. The devices will be available in a variety of fine pitch BGA (fpBGA) packages offering 144 to 601 I/O pins and will operate from 1.2volt power supplies.

Cost Optimized SERDES Architecture Provides Rich Feature Set

The LatticeECP2M family maintains all of the compelling features of the LatticeECP2 family, including DSP functionality, that are required for high-volume, cost sensitive applications. The SERDES integrated into the LatticeECP2M has been engineered specifically for implementation in a cost effective, power efficient (power consumption as low as 100mW) quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels) and supports data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip. The SERDES/PCS combination is designed to support today’s most common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless interface standards (OBSAI and CPRI).

The combination of SERDES, high performance DSP and a low cost FPGA fabric is extremely attractive to Edge and Access system vendors that are integrating these serial protocols into their wireless base stations, radio network controllers, DSLAMs and other last mile aggregation equipment that enable “triple play” technologies. Mass storage, high-speed server, medical imaging and industrial equipment system designers interested in low cost signal processing also will benefit from the LatticeECP2M family’s unique combination of features.

Features Common to the LatticeECP2M and LatticeECP2 Devices

• Optimized Logic and Routing Fabric: The logic block and routing have been optimized for today’s high performance FPGA designs and include support for distributed memory (provided on 12.5% of LUTs) and registers (provided on 75% of LUTs). 
• Pre-engineered 840Mbps Parallel I/O: Support is provided for DDR memories and other similar standards that require high-performance parallel I/O interfaces within the FPGA. These devices provide DDR mux/de-mux, precision delay and gearbox logic elements that can be combined to implement pre-engineered DDR2 (400Mbps) and other source synchronous interfaces, operating at up to 840Mbps, for applications such as SPI4.2 and ADC/DAC interfaces.
• Full Feature sysDSP™ Blocks: Embedded sysDSP blocks capable of implementing multiply, accumulate, summation and pipelining functions. The devices can implement DSP functions up to 63,000 Million Multiply Accumulates per second (MMACs).
• Easy Field Logic Update: In order to accommodate bug fixes, respond to changing standards and support the addition of new features and services, an increasing number of FPGA designs require FPGA logic updates in the field. The ECP2M devices provide dual-boot support (the ability to configure the device from two or more configurations in industry standard Serial Peripheral Interface (SPI) PROMs) and Transparent Field Reconfiguration (TransFR™) I/O to simplify field updates. TransFR I/O capability allows designers to precisely control I/O states while a new configuration is loaded into the FPGA, a significant improvement over the more conventional practice of tri-stating I/Os during reconfiguration.
• Bitstream Encryption for Enhanced Design Security: To address increasing design piracy concerns, the devices have on chip non-volatile key storage and decryption circuitry to allow the decryption of 128-bit AES encrypted bitstreams based on a unique user key. 

Design Tools and Intellectual Property Support

Design support for the LatticeECP2M devices is provided by the latest version of Lattice’s ispLEVER® design tool suite, Version 6.0 SP1. The ispLEVER design tools provide access, in one software package, to all Lattice digital devices and include synthesis support from Mentor Graphics and Synplicity. As with the LatticeSC devices, a convenient module-based GUI (graphical user interface) greatly simplifies configuring the SERDES.

Customers also will have easy access to key ispLeverCORE™ Intellectual Property modules through the IPexpress™ design flow. IPexpress-supported functions will include PCI Express, SGMII, DDR1 and DDR2 memory controllers and SPI4.2.

Availability and Pricing

Samples of the first member of the LatticeECP2M family, the LatticeECP2M-35, in both 484 and 672 ball fpBGA packages will be available in October. Lattice plans to bring the entire LatticeECP2M family to the market during the first half of 2007. The ECP2M-35 will be priced as low as $22.95 in 100,000 unit quantities for delivery in 2007.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispGDX, ispLEVER, ispLeverCORE, IPexpress, ispPAC, LatticeECP, LatticeECP2, LatticeECP2M, LatticeSC, sysDSP, sysMEM, TransFR and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

For more information contact:
Brian Kiernan, Corporate Communications Manager
Lattice Semiconductor Corporation
brian.kiernan@latticesemi.com
voice: (503) 268-8739
fax: (503) 268-8193

Original text is here