New Lattice Design Tools Deliver Comprehensive New Product Support, Innovative HDL Management Tool

-- ispLEVER 6.1 Tool Suite Supports New LatticeECP2M and
LatticeSC 90nm FPGA Families, New LatticeMico32
Open Source Microprocessor and Innovative HDL Design Management Tool --

HILLSBORO, OR - OCTOBER 23, 2006 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its ispLEVER® 6.1 programmable logic design tool suite. Version 6.1 adds new design resources and productivity enhancement tools for designers, including the innovative HDL Explorer™ tool that helps manage and analyze large FPGA designs. The ispLEVER 6.1 release supports Lattice’s latest FPGAs, including the new LatticeECP2M™ FPGA family, the new LatticeMico32™ System for 32-bit microprocessor design and enhanced third-party synthesis and simulation tools. Combined with numerous other improvements, the ispLEVER 6.1 tool suite is an extremely powerful programmable logic design solution.

“We’re excited to deliver this new tool suite in support of our revolutionary Lattice ECP2M low cost FPGA family with best-in-class memory and SERDES capability,” said Stan Kopec, corporate vice president of marketing. “Coupled with our new 32-bit open source LatticeMico32 microprocessor and the new PCI Express hard IP solution in our LatticeSC™ family, it’s easy to see why Lattice has ‘More of the Best’ FPGA solutions that are winning over new customers.”

Chris Fanning, corporate vice president of software and IP solutions, said, “The ispLEVER 6.1 tool suite extends its industry-leading timing closure capability and delivers productivity enhancements such as HDL Explorer that enable FPGA designers to complete their designs in an easy-to-use and efficient manner.”

Partners Applaud New FPGAs and Design Tools

“Synplicity's market-leading Synplify Pro© software allows designers to take full advantage of the new high-performance LatticeSC devices and the expanded memory in the LatticeECP2M FPGAs,” said Joe Gianelli, Synplicity VP of Business Development. “We believe that the Synplify Pro software's QoR, runtime and ease of use advantages will provide Lattice customers with best-in-class performance as well as cost and time to market benefits when used with these new FPGAs.”

“We are very excited about the capabilities of the new LatticeECP2M and LatticeSC families, and what they mean for our mutual customers,” said Simon Bloch, general manager, Mentor Graphics Design Creation and Synthesis Division. “With Precision® Synthesis and the ModelSim® Simulator, Mentor Graphics is the only EDA supplier supporting the full FPGA design flow. We believe that when combined with the Lattice ispLEVER 6.1 software, it creates a powerful design solution for engineers trying to solve today’s problems.”

The Design Platform for Advanced 90nm FPGA Families

The ispLEVER 6.1 tool suite continues to deliver industry-leading performance as the design platform for Lattice’s new 90nm LatticeECP2/M High Performance, Low Cost FPGA family and the LatticeSC/M Extreme Performance™ System Chip FPGA family.

The LatticeECP2M FPGA family builds on the previously released LatticeECP2™ architecture, but adds the industry’s first 3.125Gbps SERDES capability and the most dedicated embedded RAM resources in a low cost FPGA.

In addition to previously supported Gigabit and 10GB Ethernet MAC, DDR I/II, and SPI4.2 hard IP cores, ispLEVER 6.1 includes new PCI Express MACO™ support for the LatticeSCM™ family, which enables the integration of pre-engineered, high-performance IP blocks that reduce design time and cost.

The LatticeMico32 System: Tools for 32-bit Open Source Microprocessor Design

Included with the ispLEVER 6.1 tool suite, the LatticeMico32 System is used to implement the LatticeMico32 soft microprocessor and attached peripheral components in a Lattice FPGA. The LatticeMico32 core is a 32-bit Harvard, RISC architecture soft microprocessor and is available without charge for customers through an open IP core licensing agreement.

The LatticeMico32 System is based on the Eclipse C/C++ Development Tools (CDT) environment, an industry open-source development and application framework for building software. The LatticeMico32 System is comprised of two integrated tools that provide a complete solution for microprocessor design:

• The Mico System Builder (MSB) generates platform description and associated HDL for hardware implementation. GUI interfaces help the designer choose peripheral components to attach to the LatticeMico32 microprocessor and specify the connectivity between them based on the industry-standard WISHBONE bus.
• The Software Project Environment (SPE) and Debugger help the designer develop and debug code that runs on platforms created with the MSB, including program compilation, assembly, linking and debug.

HDL Explorer: A New and Innovative Tool for Managing Large Designs

New with the ispLEVER 6.1 release, the HDL Explorer tool integrates design creation, analysis, verification and documentation capabilities in a highly customizable HDL analysis environment. The HDL Explorer tool generates graphic representations of a design's hierarchical structure and connectivity based on the source HDL. The HDL Explorer tool is particularly useful for IP integration, design maintenance and re-engineering of complex FPGA HDL designs, and also helps the designer visualize higher-level abstractions of the design structure, greatly reducing the amount of time required for design management and documentation.

The HDL Explorer tool also helps the designer produce higher quality code with “linting” technology to detect common design rule faults that can, for example, cause mismatches between pre- and post-synthesis behavior.

Dozens of Improvements to All ispLEVER Tools

• The Memory Generation Tool helps create memory initialization (.mem) files.
• A new back-annotating assignments feature retains pin assignments and port attributes made by ispLEVER tools to ensure the same results in subsequent runs. 
• The Expanded Clock Boosting feature now is available for all Lattice FPGA families as well as the MachXO™ Crossover Programmable Logic Devices.
• New Process Properties include Generate X for Setup/Hold Violation, Verilog Hierarchy Separator, Register Configuration, Output Zero Frames and Search Path.
• Enhancements to the EPIC Device Editor include “undo last delete”, “unroute” and “find site by type.”
• Support for both Verilog and VHDL code generation in ispLeverDSP.
• New 16 point FFT/IFFT reference design (for use with MATLAB®/Simulink, available separately from The MathWorks). 
• The EBR Memory-Based Multiplier module implements a multiplier using RAM resources.
• An enhanced spreadsheet view in Design Planner allows editing of timing preferences in all stages of the design flow and editing of pin assignments in the post-map and pre-map stage.
• A newly added library can be used to retarget CPLD or SPLD schematic designs to an FPGA, or to use CPLD symbols in new FPGA designs.
• More than 40 HDL attributes for ispLEVER, Precision RTL Synthesis and Synplify software suites are supported as schematic symbols or net attributes.
• For LatticeSC, LatticeSCM and LatticeECP2M FPGAs, the user can apply a predefined heat sink that reduces the junction-to-ambient thermal resistance by a fixed value. The user also can adjust the junction temperature by applying a heat sink and changing the airflow value.
  

A complete list of the new features and enhancements to the ispLEVER 6.1 design tool suite can be viewed at http://www.latticesemi.com/software.

Industry Leading Synthesis and Simulation

Lattice works closely with its partners Synplicity and Mentor Graphics to provide best-in-class synthesis and simulation solutions as standard features in the ispLEVER design flow. The ispLEVER 6.1 release includes the latest updates to Synplify for Lattice 8.6.2b from Synplicity and Precision RTL 2006a.376 from Mentor Graphics. An update to the ModelSim 6.2C release also is included.

Pricing and Availability

The Windows-based ispLEVER 6.1 software that supports all Lattice digital programmable logic families is list priced an industry best value of $695 and is available now. UNIX and Linux versions also are available.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), Extreme Performance, ispLEVER, HDL Explorer, LatticeECP2, LatticeECP2M, LatticeMico32, LatticeSC, LatticeSCM, MachXO, MACO and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

For more information contact:
Brian Kiernan, Corporate Communications Manager
Lattice Semiconductor Corporation
brian.kiernan@latticesemi.com
voice: (503) 268-8739
fax: (503) 268-8193

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