Toshiba develops cost competitive MEMS packaging technologies

--Achieving world’s thinnest multi-chip MEMS package with control IC--

TOKYO--Toshiba Corporation today announced two optimized packaging technologies for micro electro-mechanical systems (MEMS) semiconductor packages that achieve significant cost reductions. The first technology covers encapsulation under normal atmospheric condition, the second a stronger structure for vacuum sealing. Both technologies can be applied at the wafer level, and both have been used to achieve multi-chip MEMS packaging with a control IC at a thickness of only 0.8mm, the thinnest yet announced. Both achievements were reported on May 28^th and 29^th (EST) at the Electronic Components and Technology Conference 2008 held at Florida, U.S.A. from May 28^th.

As achieving cost efficiency and high productivity is one of the key objectives of MEMS, there are significant demands for small sized, hermetic cavity packaging technologies. Vacuum sealing is utilized in high speed applications, such as MEMS switch and gyroscopes, but there are various problems with this, including ringing. In applications where high speed is not required, such as use in mobile phones, low cost encapsulation under normal atmospheric condition technology is employed. Toshiba has developed both packaging technologies.

Toshiba will further develop and optimize these technologies toward establishing for practical use.

Feature of development

1. Encapsulation under normal atmospheric condition
In encapsulation under normal atmospheric condition, a hermetic cavity is formed by coating a polymer sacrifice layer with SiO₂ film, etching a cavity on the sacrifice layer through holes driven through the film, and then covering the film layer with a polymer cap. Etching efficiency is increased with larger holes, but this also raises the danger of polymer inflow into the cavity. Toshiba overcame this challenge by optimizing hole size and shape, achieving increased production efficiency and preventing any inflow. Furthermore, previous applications of this technology to MEMS chips was limited to non-water-resistant covering materials, but Toshiba also achieved a moisture-resistant package through chemical vapor deposition (CVD) of a hybrid structure organic and inorganic films.

 [Package structure of encapsulation under normal atmospheric condition]

2. Vacuum sealing
In vacuum sealing, air pressure on the hermetic cavity can cause chip failure. Toshiba overcame this with application of a new corrugated encapsulation structure that increases pressure resistance. In addition, changing the shape of the etching holes from circles to ovals reduced stress and risk of damage during etching. In a further step, laminating a thicker layer extended the process to multiple level cell packaging, where high pressure resistance is essential.

[Package structure of vacuum sealing]

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